An output driver circuit (hereinafter referred to simply as a “output driver”) in an integrated circuit (LSI) generates a drive signal for a voltage-driven semiconductor switching element or the like externally connected to the LSI from an on/off signal in the LSI. The voltage-driven semiconductor switching element is, for example, an insulated gate bipolar transistor (IGBT) used in a power converter such as an inverter for variable-speed control of a motor.
FIG. 1A illustrates an example of a configuration of an output driver and a peripheral circuit.
An output signal 104 from a driver transistor circuit 101 drives an external load circuit such as a switching element not specially illustrated. The driver transistor circuit 101 includes, for example, a p-type metal oxide semiconductor field effect transistor (p-MOSFET) 101-1 and an n-MOSFET 101-2. Power supply voltage VDD is applied to the source terminal of the p-MOSFET 101-1, while the source terminal of the n-MOSFET 101-2 is grounded to ground potential VSS. The drain terminals of the p-MOSFET 101-1 and the n-MOSFET 101-2 are connected to each other. A signal net_p supplied to the gate terminal of the p-MOSFET 101-1 is asserted (set to be low level) and a signal net_n supplied to the gate terminal of the n-MOSFET 101-2 is negated (set to be low level). The p-MOSFET 101-1 and the n-MOSFET 101-2 are thereby turned on and off, respectively, to supply the voltage VDD as an output signal 104. On the other hand, the signal net_p supplied to the gate terminal of the p-MOSFET 101-1 is negated (set to be high level) and the signal net_n supplied to the gate terminal of the n-MOSFET 101-2 is asserted (set to be high level). The p-MOSFET 101-1 and the n-MOSFET 101-2 are thereby turned off and on, respectively, to cause the output signal 104 to fall to ground potential VSS.
With the change in the output signal 104 from the driver transistor circuit 101, noise (through current di/dt) is generated. Power supply noise is also generated by interaction between the driver transistor circuit 101 and the external switching element. To suppress this noise, waveforms (105, 109 in FIG. 1B) of the signal net_p and the signal net_n supplied to the p-MOSFET 101-1 and the n-MOSFET 101-2 may be rounded. This operation is performed with pre-driver circuits 102-1 and 102-2 (hereinafter referred to as “pre-driver”) that respectively generate the signal net_p and the signal net_n. The waveform of the output signal 104 from the driver transistor circuit 101 is thereby to be rounded, thus suppress the noise (through current di/dt).
In a case where the waveforms of the signal net_p and the signal net_n are simply rounded, however, the time period during which the p-MOSFET 101-1 and the n-MOSFET 101-2 are simultaneously on is increased, so that a large through current flows between power supply voltage VDD and ground potential VSS. The through current causes current noise, voltage noise, power supply noise and drop of power supply voltage. As a result, deteriorations in quality of the waveform of the output signal 104, such as a reduction in signal level of the output signal 104, a timing error due to an increase in reflection and an increase in jitter due to a change in impedance of the driver transistor circuit 101, and retardation of a rise and a fall in the waveform, are caused. Also, an increase in the through current leads to an increase in power consumption of the integrated circuit including the driver transistor circuit 101. Further, when the waveforms of the signal net_p and the signal net_n are rounded, noise tolerance during state transition is reduced.
As a first related art with respect to these problems, a method such as that illustrated in FIG. 1B is known.
In the first related art, an input signal 103 in FIG. 1A is asserted (set to be high level) at time t1, for example, to turn on the external switching element. In response to this, the pre-driver 102-1 rounds the waveform of the signal net_p so that the signal net_p is slowly asserted as indicated by 105 in FIG. 1B. On the other hand, the pre-driver 102-2 controls the waveform of the signal net_n so that the signal net_n is sharply negated as indicated by 106 in FIG. 1B. As a result, referring to FIG. 1A, at the time of, for example, turn-on of the external switching element, the n-MOSFET 101-2 is first turned off and then the p-MOSFET 101-1 is turned on. The through current between the n-MOSFET 101-2 and the p-MOSFET 101-1 is thereby suppressed, for example, when the output signal 104 rises to the turn-on level as illustrated by 107 in FIG. 1B.
On the other hand, the input signal 103 in FIG. 1A is negated (set to be low level) at time t2, for example, to turn off the external switching element. In response to this, the pre-driver 102-1 controls the waveform of the signal net_p so that the signal net_p is sharply negated as indicated by 108 in FIG. 1B. On the other hand, the pre-driver 102-2 rounds the waveform of the signal net_n so that the signal net_n is slowly asserted as indicated by 109 in FIG. 1B. As a result, referring to FIG. 1A, at the time of, for example, turn-off of the external switching element, the p-MOSFET 101-1 is first turned off and then the n-MOSFET 101-2 is thereafter turned on. The through current between the n-MOSFET 101-2 and the p-MOSFET 101-1 is thereby suppressed, for example, when the output signal 104 falls to the turn-off level as illustrated by 110 in FIG. 1B.
As described above, the first related art reduces the noise due to the through current to some extent by sharpening the pre-driver output waveform at the turn-off side. The first related art, however, has a problem that the high-speed operation of the switching element in the following stage is hindered due to rounding of the waveform of the output signal 104 output from the driver transistor circuit 101, i.e., a non-sharp rise and fall in the waveform. The influence of noise due to a change in current accompanying a change in output voltage emerges large in the vicinity of the switching threshold (Vth) of the p-MOSFET 101-1 and the n-MOSFET 101-2. In the case of the first related art, however, the signal net_p is actually rounded so as to concave in a falling portion 105 as illustrated in FIG. 1B, and the signal net_n is actually rounded so as to be convex in a rising portion 109 as illustrated in FIG. 1B. Therefore the through current is not largely reduced. Also, the rise and fall of the output signal 104 are not sharp.
FIG. 2A illustrates a configuration according to a second related art. In this configuration, the output driver includes a plurality of pairs of p-MOSFET 201-1 and n-MOSFET 201-2 (#1 to #4) implemented as a driver transistor circuit 201. Power supply voltage VDD is applied to the source terminal of each p-MOSFET 201-1 in the pairs #1 to #4. The source terminal of each n-MOSFET 201-2 in the pairs #1 to #4 is coupled to ground potential VSS. The drain terminals of the p-MOSFETs 201-1 and the drain terminals of the n-MOSFETs 201-2 are respectively coupled to each other. Output signals net_p1, net_p2, net_p3, and net_p4 from cascaded pre-drivers 202-1 (#1 to #4) are respectively supplied to the gate terminals of the p-MOSFETs 201-1 (#1 to #4). Output signals net_n1, net_n2, net_n3, and net_n4 from cascaded pre-drivers 202-2 (#1 to #4) are respectively supplied to the gate terminals of the n-MOSFETs 201-2 (#1 to #4). The output signal 204 is obtained from the junction of the drain terminals of the p-MOSFETs 201-1 and the n-MOSFETs 201-2. An input signal 203 is fed to the pre-drivers 202-1(#1) and 202-2(#1).
In this configuration, the input signal 203 in FIG. 2A is asserted at time t1, for example, to turn on an external switching element, as illustrated in FIG. 2B. In response to this, the output signals net_p1, net_p2, net_p3, and net_p4 from the cascaded pre-drivers 202-1 (#1 to #4) are sequentially asserted, as illustrated in FIG. 2B. Similarly, the output signals net_n1, net_n2, net_n3, and net_n4 from the cascaded pre-drivers 202-2 (#1 to #4) are sequentially negated, as illustrated in FIG. 2B. As a result, outputs from the pairs of the output drivers 201-1 and 201-2 (#1 to #4) are combined to obtain the output signal 204 illustrated in FIG. 2B.
On the other hand, the input signal 203 in FIG. 2A is negated at time t2, for example, to turn off the external switching element, as illustrated in FIG. 2B. In response to this, the output signals net_p1, net_p2, net_p3, and net_p4 from the cascaded pre-drivers 202-1 (#1 to #4) are sequentially negated, as illustrated in FIG. 2B. Similarly, the output signals net_n1, net_n2, net_n3, and net_n4 from the cascaded pre-drivers 202-2 (#1 to #4) are sequentially asserted, as illustrated in FIG. 2B. As a result, outputs from the pairs of output drivers 201-1 and 201-2 (#1 to #4) and combined to obtain the output signal 204 illustrated in FIG. 2B.
In the configuration illustrated in FIG. 2A, waveform characteristics of the pre-drivers 202-1 (#1 to #4) and the pre-drivers 202-2 (#1 to #4) and other factors are adjusted to perform delay control on switching of the plurality of driver transistors 201-1 and 201-2. However, changes in the waveforms of the signals net_p1, net_p2, net_p3, and net_p4, and net_n1, net_n2, net_n3, and net_n4 are not controlled. Therefore, the through current is not adequately reduced, and the rise and fall of the output signal 204 are not sharp.
In addition, the second related art requires a plurality of pairs of output drivers 201-1 and 201-2. In general, p-MOSFET 201-1 and n-MOSFET 201-2 for realizing the driver transistor circuit 201 have a large footprint. Thus, the output driver circuit in an integrated circuit according to the second related art has a problem in that its circuit scale is considerably large. For example, there is a need to mount an off chip driver (OCD) in a double data rate 2-synchronous dynamic random access memory (DDR2-SDRAM). In such a case, if the above-described second related art is used, the circuit scale may be increased and the amount of wiring in the LSI may be increased to such an extent that the design of the LSI is considerably complicated.
Japanese Laid-Open Patent Publications No. 11-234115, No. 06-177740, and No. 2001-94406 disclose further related art.